Synopsys, Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys′ comprehensive, integrated portfolio of system-level, IP, implementation, verification, manufacturing, optical and field-programmable gate array (FPGA) solutions help address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk. For more than 25 years, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems.
Requirements
1. B.Tech / M.Tech
2. Knowledge of Veriog/Systemverilog is must
3. Knowledge of VHDL is a plus
4. Sythesis, FPGA compilation knowledge/experience is a plus
5. Scripting knowledge is an advantage (Shell, Perl, Sed, awk, tcl, etc.)
To apply, click on the URL below and click ′Search openings′. Find ′India - Hyderabad′ under ′Hiring Location′ and press search button. The Requisition Number for the post is 6387BR.
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